Verilog FPGA Parts Library. Old Octavo soft-CPU project.

Universal x86 Tuning Utility for AMD Ryzen APUs on Hackintosh / macOS and Linux

BPF Processor for IDA Python

A processor cache simulator for the MIPS architecture

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

IDA Pro V850 Processor Module Extension

Disabling Intel ME on Dell Laptop

A version-agnostic ghidra plugin for de-compiling Qualcomm Hexagon QDSP6

Intel Atom C2000 series discovery tool that parses log files and returns results if a positive match is found. #nsacyber

Stream analysis for xenon TPCs

RiVer Core is an open source Python based RISC-V Core Verification framework.

Command Dispatcher, Processor, and Distributed Task Queue

Downloads ghidra processor manuals and puts them in the right folders for you automatically

A Visual RISC-V Simulator

python library to compute wind speed from GRD SAR images

5 Stage Pipelined RV32I SoC with Hardware Enforced CFI, Dual Port Synchronous Memory Controller and Bidirectional UART implemented in VHDL

AllWinnerTech Firmware and Kernel Workbench tool to unpack and pack boot.img or boot.fex of all AllWinner Tech processors allowing reverse engineering of the firmware embedded in them.

Hexagon processor module for Ghidra (not yet functional, use https://github.com/google/binja-hexagon)

Machine Learning Prediction Software Based on Classification and Regression Based on Processor [CPU] Specifications

An imaginary 16-bit CPU architecture with custom assembly language and instructions